1. Technical Field
The present invention relates generally to integrated circuits and, in particular, to a re-configurable or stitchable global clock for 3D chips.
2. Description of the Related Art
A three-dimensional (3D) stacked chip includes two or more electronic integrated circuit chips (referred to as strata or stratum) stacked one on top of the other. The strata are connected to each other with inter-strata interconnects that could use C4 or other technology, and the strata could include through-Silicon vias (TSVs) to connect from the front side to the back side of the strata. The strata could be stacked face-to-face or face-to-back where the active electronics can be on any of the “face” or “back” sides of a particular stratum.
3D integration provides modularity advantages in designing 3D systems from smaller building blocks. It enables the integration of a variety of layers/designs from different manufacturers/design-houses. In order to enable the modularity some infrastructure components such as clocking, pervasives, and power delivery are needed. However, current clock methodologies are targeted towards specific designs.
In modular 3D integration, device layers and IP blocks can come from different wafers from different semiconductor fabrication plants with significant process variations. Determining the optimal configuration at design time is inefficient, since actual silicon performance of the blocks is not available or highly uncertain. 3D integration provides new 3D clocking opportunities for low-skew synchronous clocking of blocks on different chips, but also imposes new 3D constraints such as to 3D power-supply interactions, 3D thermal interactions, and 3D input/output (I/O) limitations.